Vol. 01 · Issue 001Fri · Oct 09 · 2026
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Altera

218 live roles · semiconductor industry

We are seeking an innovative Soft CPU Design Engineer to join our IP Engineering team at our Altera Headquarters in San Jose, CA. In this specialized role, you will be responsible for the micro-architecture, RTL design, and implementation of high-performance, area-efficient Soft CPU cores. Unlike traditional ASIC design, your focus will be entirely on architecting processor pipelines that are natively optimized to leverage Altera FPGA architectures (including ALMs, embedded memory blocks, and DSP slices). You will directly shape the future of Altera's embedded processor roadmaps, such as our RISC-V-based Nios V ecosystem, enabling customers to deploy flexible, high-efficiency processing directly into programmable logic. Key Responsibilities FPGA-Targeted RTL Design: Micro-architect, design, and implement Soft CPU cores (using SystemVerilog/Verilog) intentionally structured to map efficiently onto Altera FPGA architectures

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